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February 12, 2009: SanDisk and Toshiba have announced the co-development of multi-level cell (MLC) NAND flash memory using 32-nanometer (nm) process technology to produce a 32-gigabit (Gb) 3-bits-per-cell (X3) memory chip.
Representing the third-generation 3-bits-per-cell technology on 32nm, the announcement comes within one and a half years after the introduction of the first generation of 3-bits-per-cell on 56nm, showing the rapid pace of developments in the flash memory marketplace. It will allow both companies to offer higher capacities in smaller form factors while reducing manufacturing costs.
The 32Gb X3 on 32nm technology is the smallest NAND flash memory die reported so far and is an excellent fit for the fingernail-sized microSD memory card format. Currently it is the highest density microSD memory die in the world, providing twice the capacity of a microSD chip on 43nm while still maintaining a similar die area. These factors make it ideal for high capacity storage on mobile phones.
Production for the 32nm 32Gb X3 is expected to begin in the second half of 2009. For details, visit www.sandisk.com.
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